Hardware simulation for exponential blind equal throughput algorithm using system generator

by: International Journal of Electrical and Computer Engineering (IJECE)

Publication date: 2019-02-01

Usage: Attribution-ShareAlike 4.0 International

Topics: FPGA, Hardware co-simulation, LTE Scheduling Algorithm, MATLAB Simulink, Xilinx System Generator

Collection: journals_contributions; journals

Scheduling mechanism is the process of allocating radio resources to User
Equipment (UE) that transmits different flows at the same time. It is
performed by the scheduling algorithm implemented in the Long Term
Evolution base station, Evolved Node B. Normally, most of the proposed
algorithms are not focusing on handling the real-time and non-real-time
traffics simultaneously. Thus, UE with bad channel quality may starve due to
no resources allocated for quite a long time. To solve the problems,
Exponential Blind Equal Throughput (EXP-BET) algorithm is proposed.
User with the highest priority metrics is allocated the resources firstly which
is calculated using the EXP-BET metric equation. This study investigates the
implementation of the EXP-BET scheduling algorithm on the FPGA
platform. The metric equation of the EXP-BET is modelled and simulated
using System Generator. This design has utilized only 10% of available
resources on FPGA. Fixed numbers are used for all the input to the
scheduler. The system verification is performed by simulating the hardware
co-simulation for the metric value of the EXP-BET metric algorithm. The
output from the hardware co-simulation showed that the metric values of
EXP-BET produce similar results to the Simulink environment. Thus, the
algorithm is ready for prototyping and Virtex-6 FPGA is chosen as the
platform.