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[Coursera] VLSI CAD: Logic to Layout (University of Illinois at Urbana-Champaign) (vlsicad)

by: University of Illinois at Urbana-Champaign

Publisher: Academic Torrents

Contributor: Academic Torrents

Academictorrents_collection: video-lectures

Addeddate: 2018-08-12 13:26:53

External-identifier: urn:academictorrents:ec1c86afefda42f4b36c34ae7b235ef0bfd6b9d3

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Scanner: Internet Archive Python library 1.8.1

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20.8M

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02_MiniSat_Tutorial_Video_6-11.ogv

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03_Espresso_Tutorial_Video_3-06.ogv

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ProgrammingAssignment1_jp2.zip

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65 files

SUBRIP

BACK

22.5K

01_Lecture_1.1_Welcome_and_Introduction.srt

20.7K

01_Lecture_2.1_Computational_Boolean_Algebra-_Basics_15-06.srt

22.2K

02_Lecture_2.2_Computational_Boolean_Algebra-_Boolean_Difference_15-51.srt

17.1K

03_Lecture_2.3_Computational_Boolean_Algebra-_Quantification_Operators_13-07.srt

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04_Lecture_2.4_Computational_Boolean_Algebra-Application_to_Logic_Network_Repair_16-19.srt

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05_Lecture_2.5_Computational_Boolean_Algebra-_Recursive_Tautology_9-48.srt

28.8K

06_Lecture_2.6_Computational_Boolean_Algebra-_Recursive_Tautology--URP_Implementation_20-49.srt

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01_Lecture_3.1-_BDD_Basics_Part_1_15-17.srt

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02_Lecture_3.2-_BDD_Basics_Part_2_16-51.srt

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03_Lecture_3.3-_BDD_Sharing_17-00.srt

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04_Lecture_3.4-_BDD_Ordering_28-12.srt

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05_Lecture_4.1-_SAT_Part_1_13-51.srt

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06_Lecture_4.2-_Sat_Part_2_17-56.srt

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07_Lecture_4.3-_Sat_For_Logic_25-45.srt

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01_5.1_2-Level_Logic-_Basics_9-29.srt

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02_5.2_2-Level_Logic-_the_Reduce-Expand-Irredundant_Optimization_Loop_13-06.srt

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03_5.3_Details_for_One_Step-_Expand_20-33.srt

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04_6.1_Multilevel_Logic_and_the_Boolean_Network_Model_13-57.srt

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05_6.2_Multilevel_Logic-_Algebraic_Model_for_Factoring_14-15.srt

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06_6.3_Multilevel_Logic-_Algebraic_Division_14-13.srt

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07_6.4_Multilevel_Logic-_Role_of_Kernels_and_Co-Kernels_in_Factoring_14-49.srt

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08_6.5_Multilevel_Logic-_Finding_the_Kernels_18-28.srt

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01_7.1-_Mulitlevel_Logic_and_Divisor_Extraction_-_Single_Cube_Case_14-24.srt

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02_7.2-_Mulitlevel_Logic_and_Divisor_Extraction_-_Multiple_Cube_Case_20-38.srt

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03_7.3-_Multilevel_Logic_and_Divisor_Extraction_-_Finding_Prime_Rectangles__Summary_10-46.srt

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04_8.1-_Logic_Synthesis_-_Implicit_Dont_Cares_Part_1_17-42.srt

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05_8.2-_Logic_Synthesis_-_Implicit_Dont_Cares_Part_2_11-18.srt

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06_8.3-_Logic_Synthesis_-_Satisfiability_Dont_Cares_10-50.srt

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07_8.4-_Logic_Synthesis_-_Controllability_Dont_Cares_19-59.srt

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08_8.5-_Logic_Synthesis_-_Observability_Dont_Cares_17-22.srt

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01_9.1_Basics_17-29.srt

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02_9.2-_Wirelength_Estimation_15-05.srt

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03_9.3_Simple_Iterative_Improvement_Placement_12-18.srt

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04_9.4_Iterative_Improvement_with_Hill_Climbing_15-16.srt

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05_9.5_Simulated_Annealing_Placement_21-03.srt

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06_9.6_Quadratic_Wirelength_Model_14-39.srt

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07_9.7_Quadratic_Placement_26-39.srt

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08_9.8_Recursive_Partitioning_18-15.srt

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09_9.9_Recursive_Partitioning_Example_16-28.srt

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01_10.1_Basics_19-13.srt

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02_10.2_Technology_Mapping_as_Tree_Covering_29-36.srt

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03_10.3_Tree-ifying_the_Netlist_12-07.srt

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04_10.4_Recursive_Matching_9-00.srt

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05_10.5_Minimum_Cost_Covering_16-08.srt

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06_10.6_Detailed_Covering_Example_14-28.srt

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01_11.1_Routing_Basics_17-13.srt

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02_11.2_Maze_Routing-_2-Point_Nets_in_1_Layer_16-35.srt

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03_11.3_Maze_Routing-_Multi-Point_Nets_12-24.srt

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04_11.4_Maze_Routing-_Multi-Layer_Routing_12-21.srt

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05_11.5_Maze_Routing-_Non-Uniform_Grid_Costs_14-57.srt

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06_11.6_Implementation_Mechanics-_How_Expansion_Works_23-31.srt

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07_11.7_Implementation_Mechanics-_Data_Structures__Constraints__18-02.srt

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08_11.8_Implementation_Mechanics-_Depth-First_Search_14-06.srt

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09_11.9_From_Detailed_Routing_to_Global_Routing_15-48.srt

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01_12.1_Basics_7-13.srt

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02_12.2_Logic-Level_Timing-_Basic_Assumptions__Models_30-59.srt

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03_12.3_Logic-Level_Timing-_STA_Delay_Graph_ATs_RATs_and_Slacks_27-30.srt

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04_12.4_Logic-Level_Timing-_A_Detailed_Example_and_the_Role_of_Slack_10-02.srt

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05_12.5_Logic-Level_Timing-_Computing_ATs_RATs_Slacks_and_Worst_Paths_26-55.srt

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06_12.6_Interconnect_Timing-_Electrical_Models_of_Wire_Delay_16-05.srt

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07_12.7_Interconnect_Timing-_The_Elmore_Delay_Model_14-19.srt

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08_12.8_Interconnect_Timing-_Elmore_Delay_Examples_14-56.srt

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01_KBDD_Tutorial_Video_5-20.srt

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02_MiniSat_Tutorial_Video_6-11.srt

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03_Espresso_Tutorial_Video_3-06.srt

117 files

TEXT

BACK

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01_Lecture_1.1_Welcome_and_Introduction.txt

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01_Lecture_2.1_Computational_Boolean_Algebra-_Basics_15-06.txt

14.8K

02_Lecture_2.2_Computational_Boolean_Algebra-_Boolean_Difference_15-51.txt

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03_Lecture_2.3_Computational_Boolean_Algebra-_Quantification_Operators_13-07.txt

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04_Lecture_2.4_Computational_Boolean_Algebra-Application_to_Logic_Network_Repair_16-19.txt

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05_Lecture_2.5_Computational_Boolean_Algebra-_Recursive_Tautology_9-48.txt

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06_Lecture_2.6_Computational_Boolean_Algebra-_Recursive_Tautology--URP_Implementation_20-49.txt

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01_Lecture_3.1-_BDD_Basics_Part_1_15-17.txt

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02_Lecture_3.2-_BDD_Basics_Part_2_16-51.txt

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03_Lecture_3.3-_BDD_Sharing_17-00.txt

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04_Lecture_3.4-_BDD_Ordering_28-12.txt

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05_Lecture_4.1-_SAT_Part_1_13-51.txt

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06_Lecture_4.2-_Sat_Part_2_17-56.txt

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07_Lecture_4.3-_Sat_For_Logic_25-45.txt

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01_5.1_2-Level_Logic-_Basics_9-29.txt

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02_5.2_2-Level_Logic-_the_Reduce-Expand-Irredundant_Optimization_Loop_13-06.txt

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03_5.3_Details_for_One_Step-_Expand_20-33.txt

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04_6.1_Multilevel_Logic_and_the_Boolean_Network_Model_13-57.txt

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05_6.2_Multilevel_Logic-_Algebraic_Model_for_Factoring_14-15.txt

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06_6.3_Multilevel_Logic-_Algebraic_Division_14-13.txt

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07_6.4_Multilevel_Logic-_Role_of_Kernels_and_Co-Kernels_in_Factoring_14-49.txt

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08_6.5_Multilevel_Logic-_Finding_the_Kernels_18-28.txt

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01_7.1-_Mulitlevel_Logic_and_Divisor_Extraction_-_Single_Cube_Case_14-24.txt

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02_7.2-_Mulitlevel_Logic_and_Divisor_Extraction_-_Multiple_Cube_Case_20-38.txt

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03_7.3-_Multilevel_Logic_and_Divisor_Extraction_-_Finding_Prime_Rectangles__Summary_10-46.txt

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04_8.1-_Logic_Synthesis_-_Implicit_Dont_Cares_Part_1_17-42.txt

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05_8.2-_Logic_Synthesis_-_Implicit_Dont_Cares_Part_2_11-18.txt

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06_8.3-_Logic_Synthesis_-_Satisfiability_Dont_Cares_10-50.txt

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07_8.4-_Logic_Synthesis_-_Controllability_Dont_Cares_19-59.txt

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08_8.5-_Logic_Synthesis_-_Observability_Dont_Cares_17-22.txt

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01_9.1_Basics_17-29.txt

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02_9.2-_Wirelength_Estimation_15-05.txt

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03_9.3_Simple_Iterative_Improvement_Placement_12-18.txt

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04_9.4_Iterative_Improvement_with_Hill_Climbing_15-16.txt

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05_9.5_Simulated_Annealing_Placement_21-03.txt

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06_9.6_Quadratic_Wirelength_Model_14-39.txt

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07_9.7_Quadratic_Placement_26-39.txt

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08_9.8_Recursive_Partitioning_18-15.txt

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09_9.9_Recursive_Partitioning_Example_16-28.txt

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01_10.1_Basics_19-13.txt

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02_10.2_Technology_Mapping_as_Tree_Covering_29-36.txt

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03_10.3_Tree-ifying_the_Netlist_12-07.txt

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04_10.4_Recursive_Matching_9-00.txt

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05_10.5_Minimum_Cost_Covering_16-08.txt

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06_10.6_Detailed_Covering_Example_14-28.txt

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01_11.1_Routing_Basics_17-13.txt

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02_11.2_Maze_Routing-_2-Point_Nets_in_1_Layer_16-35.txt

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03_11.3_Maze_Routing-_Multi-Point_Nets_12-24.txt

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04_11.4_Maze_Routing-_Multi-Layer_Routing_12-21.txt

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05_11.5_Maze_Routing-_Non-Uniform_Grid_Costs_14-57.txt

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06_11.6_Implementation_Mechanics-_How_Expansion_Works_23-31.txt

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07_11.7_Implementation_Mechanics-_Data_Structures__Constraints__18-02.txt

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08_11.8_Implementation_Mechanics-_Depth-First_Search_14-06.txt

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09_11.9_From_Detailed_Routing_to_Global_Routing_15-48.txt

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01_12.1_Basics_7-13.txt

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02_12.2_Logic-Level_Timing-_Basic_Assumptions__Models_30-59.txt

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03_12.3_Logic-Level_Timing-_STA_Delay_Graph_ATs_RATs_and_Slacks_27-30.txt

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04_12.4_Logic-Level_Timing-_A_Detailed_Example_and_the_Role_of_Slack_10-02.txt

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05_12.5_Logic-Level_Timing-_Computing_ATs_RATs_Slacks_and_Worst_Paths_26-55.txt

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06_12.6_Interconnect_Timing-_Electrical_Models_of_Wire_Delay_16-05.txt

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07_12.7_Interconnect_Timing-_The_Elmore_Delay_Model_14-19.txt

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08_12.8_Interconnect_Timing-_Elmore_Delay_Examples_14-56.txt

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01_KBDD_Tutorial_Video_5-20.txt

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02_MiniSat_Tutorial_Video_6-11.txt

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03_Espresso_Tutorial_Video_3-06.txt

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ProgrammingAssignment3Files.zip

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ProgrammingAssignment3Files.zip

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ProgrammingAssignment1Files.zip

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ProgrammingAssignment1Files.zip

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[Coursera] VLSI CAD: Logic to Layout (University of Illinois at Urbana-Champaign) (vlsicad)

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