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/<>-A031 203 ARMY MISSILE RESEARCH DEVELOPMENT AND ENGINEERING LAB— ETC F/G 9/5 

MICROPROCESSOR PRINTED CIRCUIT BOARDS FOR DIGITAL PROTOTYPE SYS— ETC(U) 
JUN 76 D K FRONEK, R A LANE 

UNCLASSIFIED RC-76-3 NL 



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TECHNICAL REPORT RC-76-3 



MICROPROCESSOR PRINTED CIRCUIT BOARDS 
FOR DIGITAL PROTOTYPE SYSTEMS 



D. K. Fronek and R. A. Lane S 
Systems Engineering Directorate 

US Army Missile Research, Development and Engineering Laboratory 
US Army Missile Command 
Redstone Arsenal, Alabama 35809 



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1. REPOR T NUM BER 2. GOV 

R C-76-3 I 

A. TITLE (end Subtitle) 

'MICROPROCESSOR PRINTED qiRCUIT BOARDS ' 
FOR DIGITAL PROTOTYPE SYSTEMS 

Ol '* 

7. AuTHORf#; 

D. K. Fronek and R. A./Lane 



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MUL - BEFORE COMPLETING FORM 

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Technical ^epirt T"" 1 

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RC-76-3 

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>2. REPORT DATA 

29 Jun«At76 



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US Army Missile Command AMCMS Code 2910. 23. 2570. 1.00 

ATTN: DRSMI-RC 

Redstone Arsenal, Alabama 35809 

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Commander I , OQ _ ~ 1 

US Army Missile Command ( ! . _ Juna*— /b ; 

ATTN: DRSMI-RPR .... . ''-I-tt-Wmber of pages 

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18. SUPPLEMENTARY NOTES 



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O/r 









19. KEY WORDS (Continue on reeerae aide It neceaaary and identify by block number) 

Printed circuit boards 
Digital circuits 
Dual inline package 
Integrated circuit 

20* ABSTRACT fCaottnue «i reeermm *l+e ft neceeeer y en rt Identify by block number) 

During the last year, several 4.5 in. X 6 in. printed circuit boards have 
been designed and fabricated for general and special purpose use in prototyping 
digital circuits. Since these designs represent a considerable effort, this 
report presents a descriptive overview of the various circuits and printed 
circuit boards. 



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L INTRODUCTION 



During the last year, several 4.5 in. X 6 in. printed circuit 
boards have been designed and fabricated for general and special purpose 
use in prototyping digital circuits. Since these designs represent a 
considerable effort, this report presents a descriptive overview of the 
various circuits and printed circuit boards. 



Board No 



Board Title 



Single 44-pin DIP board 
Double 44-pin DIP board 

Single 44 pin 20 in. X 16 in. matrix board 

Motorola microprocessor - less control 
and clock circuits 

Motorola microprocessor RAM (IK X 8) 

Motorola microprocessor with discrete 
clock 

Microprocessor interface P1A with rate 
generator 

Microprocessor ROM (IK X 8) Intel 1702 
Motorola microprocessor with IC clock 
General interface P1A 



N06990-A 



200039 



NO 72 02 -A 



200014 



200016B 



200025 



200030 



200031 



200035A 



200036 



The layouts for each board are found in the Appendix 



II. GENERAL PURPOSE DIP BOARDS 



A. (N06990-A and 200039) 



The increased usage of the dual inline package (DIP) 
integrated circuit (IC) has required the design of a 4.5 in. X 6 in. 
printed circuit board with standard 44-pin connector. This format 
allows both a single board design and more complicated designs using 
a "card rack" module. There are two versions of the DIP board format. 
The most common is the single 44-pin edge connector board. Occasion- 
ally, circuit signals will be generated that require more than 44 pin- 
outs on the board. A double connector DIP board format is provided for 
this function. Peripheral signals such as TTY, RS-232, etc., are con- 
veniently fed to the outside on the second edge connector. 



Both circuit board formats can easily accept sixteen 16-pin DIP 
or twenty 14-pin DIP. The predrilled hole pattern allows resistors 
(up to half-watt), capacitors, diodes, and active devices to be easily 






Fit MED 




9 

200035A 

MICROPROCESSOR 
STACK RAM, OSC 
ROM OPERAT SYS 



INTERFACE 
ADAPTER (TTY) 



integrated with the DIP IC's. Each circuit pin hole allows two addi- 
tional connections. Four power buses are provided for V cc and signal 

ground. Usually, these are assigned in pairs — front and back of the 
board. Pins 1, 22, A, and Z have been assigned for this purpose. 

More often 1 and A are tied together and assigned "+5 V." Likewise 
22 and Z are tied together and assigned "signal ground." 

B. (N07202-A) 20 in. X 16 in. Matrix Board 

The matrix board is used as a general purpose diode 
transfer circuit. Special purpose read only memories (ROM's), decoding, 
and logic functions are easily implemented on this printed circuit board 
format. Although the board is designed to house passive components, 
both V cc and signal ground are bused to one side of the board. 

C. Microprocessor Boards (200014 through 200036) (Figure 1) 

The Motorola microprocessor "chip set" has been configured 
on four 4.5 in. X 6 in. multilayer printed circuit boards. The system has 
been designed to allow easy expansion of additional memory and peri- 
pheral interface circuits. This modular concept makes this set of 
printed circuit boards extremely flexible. This series of boards makes 
easy use of the Motorola microprocessor family in a general system. 

The following block diagram shows the overall configuration. 



10 | 

200036 

GENERAL INTERFACE 
ADAPTER PIA 



20001 6B 
RAM 1 K x 8 



8 

200031 
ROM IK x 8 















D. Microprocessor Board (200035A) 

The microprocessor board is the center of processing 
activity. In addition to the microprocessing unit (MPU) M6800, a 
128 X 8 random access memory (RAM) is provided as a "stack" to support 
the interrupt activities of the microprocessor. The address of this 
stack memory is A000 through A07F (Hex). For design development 
requiring the MIKBUG operating system, a 24-pin socket is prewired to 
accept the MC6830 ROM. This ROM has been prepared at the factory to 
give the user several routines — loading, memory interrogation, printing 
a specified array, user program execution address, etc. The MIKBUG 
ROM has a prewired address at E000. Should the user wish to use other 
software for the operating system, the ROM (6830) is simply removed. 

The overall schematic diagram is shown in drawing number 200035. The 
Motorola MC6870A 2 phase clock chip (also the MC6871B) is a self- 
contained crystal oscillator providing phase 1 and phase 2 MPU signals. 
This board also contains the necessary logic to "debounce" the panel 
input switches — "Reset," "NMI," "HALT," "Single Step." 

E. Peripheral Interface Adapter Board (200030) (Figure 2) 

The Motorola peripheral interface adapter (PIA) MC6820 
is responsible for taking data from a user system and presenting it to 
the 8-bit MPU data bus. The PIA is a bidirectional device capable of 
input ing/outputing two 8-bit data registors and corresponding strobe 
signals. Because of the large number of pin-outs required for this 
device, a second 44-pin edge connector has been fabricated at the 
output side of the board. 




PIA OUTPUT 



5 





The MPU treats this device as four memory locations at 8004, 8005, 
8006, and 8007, 



8004 

8005 

8006 
8007 



DATA DIR OR 
PER REGIST 



CONTROL A 



DATA DIR OR 
PER REGIST 



CONTROL B 



During a "reset all internal PIA 
registers are set to zero. This 
coding configures the PIA as inputs 






'0 



B, 



P R ). How- 



ever, bit 2 in each control register 
must be set to a "1" to allow the 
selection of the peripheral register 
(otherwise the data direction 
register will be selected). Loading 
an "04" into 8005 and 8007 accom- 
plishes this control function. 



The PIA board also contains a rate generator, MC-14536, and the 
necessary line driver/line receiver chips to allow a teletype current 
loop or the RS-232 interface format. The rate generator must be 
adjusted to synchronize with the band rate. Pot, , is provided for 

this function. When properly set, the TTY should produce an asterisk 
(*) when "Reset" is selected from the front panel switch. (110 band 
represents a timing signal of approximately 9 msec at test point E-5). 

Optical isolators (4N33) provide a DC isolation between the MOS 
PIA and the current loop of the TTY. Jumper options allow the PIA to 
be selected as a TTY current loop device or a P.S-232 format with ± 12 V. 
The bus lines for +5 V and signal ground are directly transferred to 
the output connector to supply voltages and ground to the incoming 
circuit interface. Care should be taken not to draw excessive current 
from these lines which may be limited from the regulated +5 V supply. 
This PIA has been configured to function with the MIKBUG operating 
system. 

The MPU board and the PIA board comprise a minimum system. User 
program can be located between A04A and A07F (53 bytes). 

F. Random Access Memory Board 200016B(Figure 3) 

The RAM board contains 8 each MC6810 memory chips giving 
IK (1024) X 8 bit format. All chip decoding is done on the board 
which results in sequential memory between 0000 and 0400. Additional 
memory is available by card selecting using a 4 to 16 demultiplexer 
chip. Each card contains up to 1024 bytes of memory. Each RAM chip 
is addressed in the following manner: 




RAM 


1 


0000 


to 


007F 


RAM 


2 


0080 


to 


00FF 


RAM 


3 


0100 


to 


017F 


RAM 


4 


0180 


to 


01FF 


RAM 


5 


0200 


to 


02 7F 


RAM 


6 


0280 


to 


03 7F 


RAM 


7 


0300 


to 


03 7F 


RAM 


8 


0380 


to 


03FF 



The RAM locations are hardwired at these addresses. Address lines, 
A 10’ A ii> A 12’ A 13’ A 14’ althou S h not actively used, are provided for 
additional chip select capability. 



15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 


CARD SELECT 
ADDRESS LINES 


INTERNAL CARD ADDRESS LINES 




RAM CHIP ADDRESS 



G. Read Only Memory Board 200031 (Figure 4) 

A IK X 8 ROM array (UV erasable) is provided on this 

card. Decode logic is provided with one 74C04 inverter chip and a 

74C30 eight input NAND gate. Address lines A 0 through A, are available 

o 13 

on the board and are to be selected by the user. Absolute addressing 
is available with the limit of six inverting inputs. 



15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 


CHIP SELECT 
ADDRESS 


ROM CHIP 
ASSEMBLY 



t 



7 














An example of a ROM array follows: 

SELECT ROM 1 AT EOOO THROUGH EOFF 
ROM 3 AT FFOO THROUGH FFFF. 




Intel 1702 programmable read only memories (PROM) are used on 
this board. A -9 V supply is required for normal read operation. 
Currently, there is no UV-PROM device that does not require a negative 
voltage in addition to +5 V (typically). It is assumed that programming 
of the PROM is done elsewhere — the program line is hardwired in the 
"read" mode of operation. 

These four boards (MPU, PIA, RAM, ROM) constitute a small working 
microcomputer. One thousand bytes of RAM and ROM will allow many 
adequate solutions of arithmetic and logical control problems. Addi- 
tional PIA boards will increase the peripheral flexibility while addi- 
tional memory will allow more complex user programs. Currently there 
are several working systems using this machine concept. For additional 
flexibility the following microprocessor printed circuit boards are 
available: 

1) 200014 - MPU, PIA, RAM, ROM less clock and control 

2) 200025 - MPU, Stack, ROM with discrete clock 

3) 200036 - General PIA interface board. 



8 




H. Microcomputer Subsystem 200014 (Figure 5) 

This single 4.5 in. X 6 in. board is intended to be 
used with a "piggy back" printed circuit board having the additional 
pin outs necessary to interface the PIA teletype and the external clock 
and control signals. The MIKBUG resident operating system is assumed 
to be used. Additional ROM (6830) space has been provided with the 
chip selects at the option of the user. A RAM stack and a program RAM 
is also available - chip selects are at the option of the user. 

This board was an early version of the microprocessor system and 
does not have the flexibility of easy expansion. The entire system 
can be constructed on this board and the "piggy back" card attached to 
the system board. 

I. Microprocessing Unit - Discrete Clock Board 20025 (Figure 6) 



This MPU board closely approximates the MPU 200035A 
board. The exception being that of a discrete clock. There may be a 
reason to run the microcomputer at clock speeds slower than the fixed 
frequency offered by the MC6871B crystal oscillator IC. A slower clock 
frequency can allow more memory (increased capacitance) to respond to 
the bus system without data and address buffers. A dual monostable 
multivibrator (9602) generates the nonoverlapping clock signals at a 
frequency determined by timing components R^, R^, , C^. Phase 1 and 

phase 2 clock signals are processed through the NPN-PNP transistor 
driver stage (Q^, C^, Q^> Q^). The l eve ls at the output of this stage 

are very near V cc > 5 V. The high voltage is required by the MPU for 

proper clocking. Bus phase 2 is buffered and sent to the control bus 
for distribution. 

Control logic to "debounce" switch inputs is also contained on 
this board to perform "Reset," "Halt," "NMI," and "Single Step." 

J. General Peripheral Interface Board, PIA - 200036 (Figure 7) 



The PIA MC6820 interface adapter is the primary parallel 
device that communicates with the external world. The user has the 
option of two 8-bit data ports that can be configured as inputs or out- 
puts in any combination (16 inputs, 15 inputs - 1 output, 14 inputs - 
2 outputs, ... 16 outputs). There are additional control signals that 
may be configured as inputs or outputs from program control. This board 
contains the address bus; control functions, V and signal ground in a 



double 44-pin edge connector format. The user must choose chip selects, 
and provide external conductor paths from the PIA to the external cir- 
cuits. The remainder of the general PIA board is configured as a DIP 
prototype format. Up to twelve 16-pin Dip's or fifteen 14-pin DIP IC's 
may be used on this board. Rate generators, buffers, decode logic, and 
other interface circuits may be especially implemented on this board. 






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Figure A-4. Motorola MPU-less control and 
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Figure A~5. Motorola MPU RAM (IK X 8). 







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Figure A-7. MPU interface PIA with rate generator 




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Figure 10. (Concluded) 




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US Army Materiel Development and Readiness Command 
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DRCDL 

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-R, Dr. McDaniel 
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-RPR (Record Set) 

(Reference Copy) 



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