NASA Technical Reports Server (NTRS) 20090011885: Customizable Digital Receivers for Radar

Technology Focus: Sensors

Customizable Digital Receivers for Radar

These receivers are unusually compact and versatile.

NASA’s Jet Propulsion Laboratory, Pasadena, California

Compact, highly customizable digital
receivers are being developed for the
system described in “Radar Inter-
ferometer for Topographic Mapping of
Glaciers and Ice Sheets” (NPO-43962),
NASA Tech Briefs , Vol. 31, No. 7 (August
2007), page 72. In the original in-
tended application, there is a require-
ment for 16 such receivers, each dedi-
cated to, and mounted directly on, one
antenna element in a 16-element array.
The receivers are required to operate
in unison, sampling radar returns re-
ceived by the antenna elements in a dig-
ital beam-forming (DBF) mode. The
design of these receivers could also be
adapted to commercial radar systems.
At the time of reporting the informa-
tion for this article, there were no com-

mercially available digital receivers ca-
pable of satisfying all of the operational
requirements and compact enough to
be mounted directly on the antenna el-
ements.

The figure depicts the overall system
of which the digital receivers are parts.
Each digital receiver includes an analog-
to-digital converter (ADC), a demulti-
plexer (DMUX), and a field-program-
mable gate array (FPGA). The ADC
effects 10-bit band-pass sampling of
input signals having frequencies up to
3.5 GHz. (In the original intended appli-
cation, the input signals would be inter-
mediate-frequency signals obtained
through down-conversion of signals
from a radio frequency of several tens of
gigahertz.) The input samples are de-

multiplexed at a user-selectable rate of
1:2 or 1:4, then buffered in part of the
FPGA that functions as a first-in/ first-out
(FIFO) memory. Another part of the
FPGA serves as a controller for the ADC,
DMUX, and FIFO memory and as an in-
terface between (1) the rest of the re-
ceiver and (2) a front-panel data port
(FPDP) bus, which is an industry-stan-
dard parallel data bus that has a high-
data-rate capability and multichannel
configuration suitable for DBF.

Still other parts of the FPGA in each
receiver perform signal-processing func-
tions. The design exploits the capability
of FPGAs to perform high-speed pro-
cessing and their amenability to cus-
tomization. There is ample space avail-
able within the FPGA to customize it to

Digital Receivers in an array sample and preprocess input signals from antenna elements. The receiver outputs are coupled in turn onto the parallel
data bus.

NASA Tech Briefs, August 2008

5

implement such application-specific,
real-time processes as digital filtering
and data compression. To afford addi-
tional operational flexibility and to en-
able use of a receiver in other applica-
tions, the design also includes a
provision for an additional “drop-in” cir-
cuit board containing analog amplifica-
tion and filtering circuitry. Such boards,
which are relatively simple and inexpen-
sive, can be easily exchanged by the user
to modify center-frequency, bandwidth,
and signal-level parameters.

The digital receivers can be configured
to operate in a stand-alone mode, or in a
multichannel mode as needed for DBF. In
the multichannel/DBF mode, the receivers
are made to take turns in transmitting sam-
pled data onto the bus. The bus port on
each receiver adheres to the FPDP-II stan-
dard, which supports an aggregate data
rate of 400 MB/s. While the primary role
of the FPDP bus is to transmit sampled
data from receivers to a data-storage unit,

the bus can also be used to transmit config-
uration data to the receivers. The bus also
enables the receivers to communicate with
one another — a capability that could be
useful in some applications. Each receiver
is also equipped with an RS-232 interface,
through which configuration data can be
communicated.

The data on the bus are aggregated
and then sent to a data-acquisition
(DAQ) subsystem by means of a serial
FPDP interface that, like each receiver,
contains an FPGA that serves partly as a
FIFO memory and partly as a control
unit. The DAQ subsystem stores the data
onto a hard-disk array for postprocess-
ing. In its role as a control unit, this
FPGA sends timing and configuration
information to each of the 16 receivers.

Although band-pass sampling is a
widely applied technique, heretofore, it
has been little used in radar systems.
The use of band-bass sampling in the
present receiver design is what makes it

possible to achieve compactness: Band-
pass sampling makes it possible to feed,
as input to the ADC, signals having
higher frequencies than could otherwise
be utilized. In so doing, band-pass sam-
pling enables elimination of an addi-
tional down-conversion stage that would
otherwise be needed, thereby reducing
the design size of the receiver. This de-
sign approach also eases filtering con-
straints and, in so doing, reduces the re-
quired sizes of filters.

The customizability of the receiver
makes it applicable to a broad range of
system architectures. The capability for
operation of receivers in either a stand-
alone or a DBF mode enables the use of
the receivers in an unprecedentedly
wide variety of radar systems.

This work was done by Delwyn Moller,
Brandon Heavey, and Gregory Sadowy of
Caltech for NASA’s Jet Propulsion Laboratory.
For more information, contact iaoffice@
jpl.nasa.gov. NPO-45539

® Two-Camera Acquisition and Tracking of a Flying Target

An unanticipated moving target can be automatically spotted and tracked.

NASA’s Jet Propulsion Laboratory, Pasadena, California

A method and apparatus have been
developed to solve the problem of au-
tomated acquisition and tracking,
from a location on the ground, of a lu-
minous moving target in the sky. The
method involves the use of two elec-
tronic cameras: (1) a stationary cam-
era having a wide field of view, posi-
tioned and oriented to image the
entire sky; and (2) a camera that has a
much narrower field of view (a few de-
grees wide) and is mounted on a two-
axis gimbal. The wide-field-of-view sta-
tionary camera is used to initially
identify the target against the back-
ground sky. So that the approximate
position of the target can be deter-
mined, pixel locations on the image-
detector plane in the stationary cam-
era are calibrated with respect to
azimuth and elevation. The approxi-
mate target position is used to initially
aim the gimballed narrow-field-of-view
camera in the approximate direction
of the target. Next, the narrow-field-of
view camera locks onto the target
image, and thereafter the gimbals are
actuated as needed to maintain lock
and thereby track the target with preci-
sion greater than that attainable by use
of the stationary camera.

Figure 1 shows a prototype of the ap-
paratus. The stationary, wide-field-of-
view camera includes a fish-eye lens
that projects a full view of the sky (the
full 360° of azimuth and the full 90° of
elevation) onto a 5 12x5 12-pixel image
detector of the active-pixel-sensor type.
The gimballed narrow-field-of-view
camera contains a charge-coupled-de-
vice (CCD) image detector. The appa-
ratus also includes circuitry that digi-
tizes the image-detector outputs and a

computer that processes the image
data and generates gimbal-control
commands.

The stationary, wide-field-of-view cam-
era repeatedly takes pictures of the sky.
In processing of the image data for each
successive frame period, the immediately
preceding frame is subtracted from the
current frame, so that all that remains in
the image is what has changed between
the two successive frames. Hence, if
there is a moving luminous target, it

Figure 1. This Prototype Apparatus was built and tested, yielding the images shown in Figure 2.

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NASA Tech Briefs, August 2008