General Instrument SP0264 Narrator Speech Processor Data Sheet

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GENERAL

INSTRUMENT PRELIMINARY INFORMATION

Narrator Speech Processor

FEATURES

ш Natural speech

m Standalone operation with inexpensive support PIN CONFIGURATION
components Top View

ш Wide operating voltage
ш Word, phrase, or sentence library, ROM

expandable
Ш Expandable to 448K of ROM directly 26 |] ROM CLOCK
m Simple interface to most microcomputers or 25 |0 SBY RESET
microprocessors 24 [7 DIGITAL OUT

Supports L.P.C. Synthesis; Formant Synthesis;
and Allophone Synthesis

ш 28 pin dual in line package

ш Available іп -40°C to +85°C version, 5Р02641 21 | SER IN

GENERAL DESCRIPTION

The SP0264 Speech Processor (SP) is a single
chip N-Channel MOS LSI device that uses its stored
program to synthesize speech or complex sounds.

The achievable output is equivalent to a flat fre-
quency response ranging from 0 to 5KHz, а
dynamic range of 42dB, and a signal-to-noise ratio
of approximately 35dB.

The SP0264 incorporates four basic functions:

m A software programmable digital filter that can be APPLICATIONS
made to model a VOCAL TRACT. m Telecommunications m Warning systems
M A64K ROM that stores both data and instruc- m Appliances | m Security systems
tions (THE PROGRAM). . Computer peripherals IB Electronic musical
и AMICROCONTROLLER that controls the ο. ο ποπ
data flow from the ROM to the digital filter, the = Torona compere: Modelo menina
9 , m Toys/Games m Narrow bandwidth

assembly of the "word strings" necessary for
linking speech elements; and the amplitude and
pitch information to excite the digital filter.

В A PULSE WIDTH MODULATOR that creates а
digital output that is converted to an analog
signal when filtered by an external low-pass filter.

W Educational aids m Communication systems

005968
S968 GE

© 1986 General Instrument Corporation DS50012B-1

GENERAL

INSTRUMENT SP0264

CS
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OPERATION DESCRIPTION

The addressing of the SP0264 is controlled by the
address pins (A1-A8), Address load (ALD), and Strobe
Enable (SE). Speech data for the SP0264 сап be
stored within the internal 64K ROM and/or an external
serial speech ROM.

There are two modes available for loading an address
into the chip. Strobe Enable (SE) controls which mode
will be used.

Mode 0 (SE = 0). The speech processor will latch an
address when any one (or more) address pin makes a
low-to-high transition. All address lines must be
returned to the low state prior to entering a new
address. (NOTE: Address zero (0000 0000) is not a
valid address in this mode of operation.) In order to
best utilize this mode of operation, a vocabulary
should consist of no more than eight individual words
or phrases such that single address line transitions
can be made. These words or phrases must be stored
using the following entry point address: 1, 2, 4, 8, 16,
32, 64 and 128.

NOTE: There is a 2-byte overhead penalty paid for
each dummy entry point between the entry points
actually used.

Mode 1 (SE = 1). The SP0264 will latch an address
using the ALD pin. The desired address is set up on
the address bus (A1-A8) and then ALD is pulsed low.
Any address can be loaded using this mode, but
certain set up and hold times are required (refer to the
timing diagrams for the specific times).

Two microprocessor interface pins are available for
loading of addresses using mode 1. They are LRQ and

SBY. Load Request (LRQ) tells the processor when
the address input buffer is full. Standby (SBY) tells
the processor that the chip has stopped talking and no
new address has been loaded.

When LRQ is low, a new address can be loaded onto
the address bus. Strobing ALD will cause the new
address to be loaded and LRQ to go high. LRQ will
return low when the address buffer is available to
accept a new address. The SP0264 is capable of
latching one new address while speaking the last
utterance (word or phrase). The time between address
load requests is variable, depending on the length of
the utterance currently being spoken.

Standby (SBY) goes low when an address is loaded
and will stay low until all internal instructions have
been completed (i.e., the speech chip stops talking).
If a second address has been loaded before the chip
stops speaking the first utterance, SBY will stay low
through the completion of the second utterance (ad
infinitum).

The SP0264 may be partially powered down when SBY
is high to conserve battery life, provided VD1 remains
powered. During power down and power up, reset
should be held low to ensure the proper reset
condition. While the speech processor is in the partial
power down state, the handshake control signals
(ALD, SE, LRQ, and SBY) and the address bus are
active. However, the SP0264 will not output the
addressed speech data until after Vpp is reapplied.

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DS50012B-2

GENERAL SP0264

INSTRUMENT

BLOCK DIAGRAM

СІ 8 BITS
XTER ROM DISABLE SOURCE AND

c2 5 ο INTERPOLATION

C3 ROM CLOCK (5 REGISTERS)

SER

OUT
SERIAL COEFFICIENT TRANSFER 12 HOLDING
ALU REGISTERS
(COEFFICIENTS)
8 BITS
VOCAL TRACT MODEL
SER DATA (12 POLE DIGITAL
IN FILTER)
7 BITS
8K x 8-BIT PULSE WIDTH
«Μαν ЩО бие
OSC 2

ADDRESS

REGISTER
START ADDRESS HANDSHAKE
LATCH МН CONTROL

Nee — 2 ALD SE LRQ SBY VD1
te 8-BIT 2:
ADDRESS SBY RESET

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DS50012B-3

GENERAL

INSTRUMENT

PIN FUNCTIONS

PIN NUMBER NAME FUNCTION
1 (power supply) Vss Ground
2 (input) RESET A logic 0 resets the speech processor. Must be returned to

a logic 1 for normal operation. Upon reset C1, C2, C3, and
SER OUT go to "0", and SBY goes to "1."

3 (input) ROM DISABLE For use with an external serial speech ROM. A logic 1
disables the external ROM.

4,5,6 (outputs) C1,C2,C3 Control lines for use with an external serial speech ROM.

7 (power supply) VDD

8 (output) SBY STANDBY. A logic 1 output indicates that the SP is inactive

and Vpp can be powered down externally to conserve
power. Whenthe SP is reactivated by an address being
loaded, SBY will go to a logic O.

|

9 (output) LRQ LOAD REQUEST. LRQ is a logic 1 output whenever the
: input buffer is full. When LRQ goes to a logic 0, the input
port is loaded by placing the 8 address bits on A1-A8 and

pulsing the ALD input.

10,11,13,14 A8,A7,A6,A5 8-bit address that defines any one of 256 speech

15,16,17,18 (inputs) A4,A3,A2,A1 entry points.

12 (output) SER OUT SERIAL ADDRESS OUT. This output transfers a 16-bit_
address serially to an external speech ROM. When SBY
RESET and RESET go to "0", SER OUT goes to "0". When
SBY RESET goes to "0" SER OUT goes to "O".

19 (input) SE STROBE ENABLE. Normally held in a logic 1 state. When
tied to ground, ALD is disabled and the SP will automatically
latch in the address on the input bus approximately 1 us
after detecting a logic 1 on any address line.

20 (input) ALD ADDRESS LOAD. A negative pulse on this input loads
the 8 address bits into the input port. The negative edge
of this pulse causes LRQ to go high.

21 (input) SER IN SERIAL IN. This is an 8-bit serial data input from an
external speech ROM.

22 (input) TEST A logic 1 places the SP in its test mode. This pin should be
normally grounded.

23 (power supply) VD1 Standby power supply for the interface logic and controller.

24 (output) DIGITAL OUT Pulse width modulated digital speech output which, when

filtered by a 5KHz low-pass filter and amplified, will drive

a loudspeaker.
ὨΕὣΠὉὓᾷἋπὌ--ΠἹπΓΝΝΝ" <<< — ——
DS50012B-4

GENERAL $р0264

INSTRUMENT

PIN FUNCTIONS (Continued)

PIN NUMBER NAME FUNCTION

25 (input) SBY RESET STANDBY RESET. A logic 0 resets the interface logic.
Normally should be a logic 1. SBY RESET must be tied to
RESET (pin 2).

26 (output) ROM CLOCK This is a 1.56MHz clock for an external serial speech ROM.

27 (input) OSC 1 ХТА! IN. Input connection for a 3.12MHz crystal.

28 (output) OSC2 XTAL OUT. Output connection for a 3.1 2MHz crystal.

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DS50012B-5

GENERAL SP0264

INSTRUMENT

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ELECTRICAL CHARACTERISTICS/SP0264

Maximum Ratings*

All pins with respect to Vss.................. -0.3 to 8.0V
StorageTemperature..................... -25°C to 125°C
Standard Conditions

Clock — Crystal Frequency................... 3.120 MHz
Operating Temperature............. TA» 00C to +70°C

DC CHARACTERISTICS/SP0264

*Exceeding these ratings could cause permanent
damage to the device. This is a stress rating only and
functional operation of this device at these conditions
is not implied. Operating ranges are specified in
Standard Conditions. Exposure to absolute maximum
rating conditions for extended periods may affect
device reliability.

Data labeled "typical" is presented for design guidance
only and is not guaranteed.

Characteristic [Sym | Min | Typ | Мах | Units | Conditions
- 6.5 V

Primary Supply Voltage Vpp 4.5
Standby Supply Voltage М
Primary Supply Current Іор
Standby Supply Current Ip
INPUTS τ(
A1-A8, ALD, SER IN,
TEST, SE
LOGIC 0 Ма.
LOGIC 1 Мн
САРАСІТАМСЕ Cin
LEAKAGE 1
RESET, SBY RESET
LOGIC 0 VnsiL
LOGIC 1 Мн
OUTPUTS

SBY, Digital Out, C1, C2,
C3, LRQ, ROM DIS,
ROM CLK, SER OUT

LOGIC 0 Vor
LOGIC 1 Vou
OSCILLATOR
OSC 2 (Output)
LOGIC 0 VoL
LOGIC 1 Vou
Short Circuit Current Ise
on OSC2
OSC1 Input Current lin

05500128-6

RESET and SBY RESET high.
OSC1 =3.12 MHz. All other inputs
floating.

Same as above.

0 volts bias, f = 3.12 MHz
γρινΞ 7.0V Other Pins = 0.0V

Vpi = 4.5V
Vp: = 6.5V

lo, = 0.72mA (215 TTL Loads)
Іон = “SOLA (2LS TTL Loads)

When driven from external input
OSC1 (Input) = 4.00V MIN at
Vp; = 4.50V

OSC1 (Input) = 0.60V MAX

OSC1 (Input) = 0.60V
OSC2 (Output) = 0.00V

OSC1 (Input) = 0.00V

GENERAL 5Р02641

INSTRUMENT

ELECTRICAL CHARACTERISTICS/SP0264I

Maximum Ratings*

All pins with respect to Vss.................... -0.310 8.0V
StorageTemperature....................... -259C to 1259C

Standard Conditions

Clock — Crystal Frequency...................... 3.120 MHz
Operating Temperature.............. TA» -409C to +85°C

*Exceeding these ratings could cause permanent
damage to the device. This is a stress rating only and
functional operation of this device at these conditions
is not implied. Operating ranges are specified in
Standard Conditions. Exposure to absolute maximum
rating conditions for extended periods may affect
device reliability.

Data labeled "typical" is presented for design
guidance only and is not guaranteed.

DC CHARACTERISTICS/SP0264l (T, = -40°C to +85°C)

Characteristic

Primary Supply Voltage Vpp

Standby Supply Voltage Ми -
Primary Supply Current lbp
Standby Supply Current Ірі
INPUTS τ
A1-A8, ALD, SER IN,
TEST, SE
LOGIC 0 Μι
LOGIC 1 Мн
САРАСПАМСЕ Сн
LEAKAGE L
RESET, SBY RESET
LOGIC 0 VnsiL
OUTPUTS

SBY, Digital Out, C1, C2,
C3, LRQ, ROM DIS,
ROM CLK, SER OUT

LOGIC O VoL
LOGIC 1 Vou
OSCILLATOR
OSC 2 (Output)
LOGIC 0 VoL
LOGIC 1 Vou
Short Circuit Current lsc
on OSC2
OSC1 Input Current ἦν

- 6.5 V

RESET and SBY RESET high.
OSC1 = 9.12 MHz. All other inputs
floating.

Same as above.

0 volts bias, f = 3.12 MHz
VpIN = 7.0V Other Pins = 0.0V

Vpi = 4.5V
Vpi = 6.5V

lg, = 0.72mA (215 TTL Loads)
Іон = -5ΟμΑ (215 TTL Loads)

When driven from external input
OSC1 (Input) = 4.00V MIN at
Vp; = 4.50V

OSC1 (Input) = 0.60V MAX

OSC1 (Input) = 0.60V
OSC2 (Output) = 0.00V

OSC1 (Input) = 0.00V

05500128-7

GENERAL SP0264

INSTRUMENT

AC CHARACTERISTICS

ALD
A1 - A8 Set Up
Hold
LRQ
SBY

сво
SBY

AC CHARACTERISTICS
CONDITIONS

ALD > 960ns

A1 - АЗ Set Up
Hold

LRQ

SBY

ALD I
з те |

! Ι
ΜΝ —
INTERNAL ALD 320ns |
! MI— ADDRESS LATCHED ON INTERNAL ALD RISING EDGE
MAX
INTERNAL ALD geons | |

in1—9 ADDRESS HOLD TIME AFTER MAX INTERNAL ALD
Ἰερμε-Ρρίά--- 'һ2
A1-A8 I
|
— - {раї
LRQ i
Ц

DS50012B-8

GENERAL SP0264

INSTRUMENT

AC CHARACTERISTICS

CONDITIONS

Address Buffer ready
for next load.

TYPICAL TIMING SEQUENCE

SBY RESET,
RESET

LD

PROCESSOR CAN LOAD DATA ANY
TIME AFTER LRQ GOES LOW.

TRA Ц
[Πα И START OF SECOND
tod3 SEQUENCE.
SBY
+-- START OF FIRST SPEECH SEQUENCE. |
%

AC CHARACTERISTICS

CONDITIONS

Ce qw ues

Clock F 3.11 3.120 | 3.13 MHz
Clock Duty Cycle - 48 - 52 %
RESET, SBY RESET | 1,2 25 - - ps

SBY RESET, RESET
— Re

Crystal oscillator driven
from external.

DS50012B-9

GENERAL SP0264

INSTRUMENT

EXTERNAL ROM INTERFACE TIMING

ROM CLOCK (22)
(1.56MHz)

2 А
(7 е LU τ τ
T [ο |в Де Де То.

PC LOAD | ASR LOAD DSR SHIFT OUT
DSR LOAD |
RET REG LOAD |
|

RET

G31dAVS

p———————————————————————————————————————— ——
DS50012B-10

GENERAL

INSTRUMENT

AC CHARACTERISTICS

CONDITIONS

Access time

Serial in setup time

ROM CLOCK

C1, C2, C3
SEROUT

ROM CLOCK

SERIAL IN

ἱβρίη

Sent OR
DS50012B

INSTRUMENT

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SP0264 EXTERNAL AND INTERNAL CONTROL LINES*
(ALL SYNCHRONOUS ΤΟ THE ROM CLOCK)

сї са оз
0 0 0 МОР- No Action Taken

0 0 1 ASRLD - (Address Shift Register Load)
Serially shifts data (MSB first) from the serial address out pin
(also occurs internally in the SP0264) into the ASR reg in
preparation for loading into the PC. The ASRLD loads the 16 bits
of the ASR with two 8-bit load sequences followed shortly by
PCLD.

0 1 0 PCLD - Loads the contents of the ASR register into the PC. Occurs only
after 16 ASRLDS have occurred.

0 1 1 DSRLD - (Data Shift Register Load)
Loads the 8 bit data shift register with the contents of the ROM
pointed to by the current address in the PC. The DSRLD will also
shift out the LSB of the 8 bit DSR and increment the PC.

1 0 0 DSRSH - (Data Shift Register Shift)
Shifts data out of DSR reg starting with the second LSB (the first
LSB is shifted out with the occurrence of aDSRLD). There are
seven (7) DSRSH's after every DSRLD (not necessarily
consecutive).

1 0 1 STACKLD- Loads the STACK with the current value of the PC.

1 1 0 RETURN - Loads the PC with the contents of the STACK.

1 1 1 Op Code not implemented.

"ΑΙ ROMs including the SP0264 internal ROM will be activated by the above control lines. However only the ROM
with the current chip select will be enabled to send speech data to the SP0264.

[AE ы <<<<< Есенинни
0550012В-12

GENERAL SP0264

INSTRUMENT

TYPICAL APPLICATION STANDALONE CONFIGURATION

AUDIO AMP

45V

SBY RESET
Vgs TEST

*Diode possibly necessary if power is turned off then on in less than 50ms.

e—a
DS50012B-13

GENERAL SP0264

INSTRUMENT

TYPICAL APPLICATION MICROCOMPUTER INTERFACE

%5у
AUDIO АМР

10.11.13

100

EXTERNAL SERIAL SPEECH ROM

SPEECH PROCESSOR
(OPTIONAL)

ESENE E Еа и E SASE RAE RL ENTE TD
DS50012B-14

GENERAL

INSTRUMENT

TEST MODES
The TEST pin (22) should be kept grounded at all times Returning TEST to 0 will not rescind this mode unless
to avoid entering any test mode accidentally. RESET is pulsed.

INTERNAL ROM DISABLE

This mode may be entered by wiring TEST to a —— 4

permanent high and pulsing RESET. This causes the RESET NNE T Т ғ.

5Р0264 to ignore its internal ROM. Instructions must

be supplied serially through pin 21 (Serial Data In). The ΕΕ.
0

chip should be interfaced to an SPROOO to fully utilize
this mode.

TEST

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DS50012B-15

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"The information in this publication, including schematics, is suggestive only.
General Instrument Corporation does not warrant, nor will be responsible or GENERAL
liable for, (a) the accuracy of such information, (b) its use or (c) any infringement INSI р UM ENT

of patents or other rights of third parties."

DS50012B-16